Design of a single chip CMOS RF GFSK receiver with a dll-based demodulator

Abstract

A new GFSK demodulator with a digital offset canceller is proposed. This demodulator recovers the binary data by detecting the period difference of FSK modulated signals. For detection, it used only a DLL and edge detecting DFFs, and so can be implemented low power. Moreover, the demodulator does not need additional filters for the purpose of reducing harmonic interference, which are essentially the required blocks for differential demodulators or quadrature demodulators. As a result, this demodulator consumes only 2mA from 1.8V supply. The measured SNR for 0.1% BER is 20dB. In addition, a new offset canceller for the proposed demodulator is also proposed and implemented. This offset canceller measures and compensates offset in two symbol periods. Finally, a single chip 2GHz CMOS RF GFSK receiver is implemented in a low IF architecture. Their system specification is derived from the Bluetooth standard. For the input sensitivity of -70dBm, 24dB system NF, -16dBm system IIP3, 20dB IIR for the receiver should be satisfied to achieve 0.1% BER. All other building blocks, such as RF front end, channel select filter, limiter/RSSI, are implemented based on the derived specifications. Some design techniques for each block is presented. The measured sensitivity of the implemented receiver is -78dBm and the maximum usable level is -16dBm. The die size is 6㎟ and the IC draws 25mA from 3V system supply. The receiver was implemented using 1P6M 0.18um CMOS process enhanced for RF circuits. MIM option and thick metal option were used.