Resource-constrained low power bus encoding in embedded system design

Abstract

Minimizing power consumption of a bus is one of the most important design objectives in embedded system-on-chip (SoC) design and ultra deep-submicron (UDSM) technology. In this thesis, we address the problem of design space exploration of low-energy software bus encoding in embedded SoC design. Traditionally, finding a bus encoding that leads to a minimum energy consumption of a bus has been an important research issue, but relatively little attention has been paid to the cost of software encoding implementation. In embedded system design, the memory space for storing the encoding information is strictly limited. Consequently, exploring bus encoding implementation alternatives under such constraint becomes very necessary and/or useful. Also, with the move to silicon processes of 0.18 micron and below, crosstalk delay is becoming the first-order problem in dynamic power consumption as well as in signal integrity. Caused by capacitive coupling between adjacent wires, crosstalk can change the delay of a signal or result in an incorrect logic transition, leading to a chip malfunction or a failure. In this thesis, we propose a systematic design space exploration algorithm for low-power bus encoding which completely eliminates the crosstalk delay. From experiments on a set of benchmark designs, the proposed algorithm was shown to consume 48% less power consumption on average over existing techniques with relatively little memory overhead.