(An) integrated algorithm for memory allocation and mapping in high-level synthesis

Abstract

With the increasing design complexity and performance requirement, data arrays in behavioral specification are usually mapped to fast on-chip memories in behavioral synthesis. In this paper, we over-come two limitations of the previous works on the problem of memory-allocation and array-mapping to memories. Specifically, our key features are (1) a tight link to the scheduling effect, which was totally or partially ignored by the existing memory synthesis systems, and supporting (2) nonuniform access speeds among the ports of memories, which greatly diversify the possible (practical) memory configurations. To support this, we propose an efficient approach which solves features (1) and (2) in an integrated fashion to explore memory configurations more fully and effectively. Experimental data on a set of benchmark filter designs are provided to show the effectiveness of the proposed exploration strategy in finding globally best memory configurations.