Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-addersCSA를 이용한 회로속도와 면적의 상관관계 정밀측정을 통한 연산최적화

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dc.contributor.advisorKim, Tae-Whan-
dc.contributor.advisor김태환-
dc.contributor.authorKim, Young-Tae-
dc.contributor.author김영태-
dc.date.accessioned2011-12-13T06:01:32Z-
dc.date.available2011-12-13T06:01:32Z-
dc.date.issued2001-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=165848&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/34436-
dc.description학위논문(석사) - 한국과학기술원 : 전산학전공, 2001.2, [ iv, 25 p. ]-
dc.description.abstractTiming and area of circuits are two of the most important design criteria to be optimized in data path synthesis. In addition, carry-save adder(CSA) cell has been proven to be one of the most efficient implementation units in optimizing timing and/or area of arithmetic circuits. However, the existing approaches are restricted in using CSAs, i.e., optimizing each operation tree separately without any interaction between them, leading to a locally optimized resultant CSA circuits. To overcome the limitation, we propose a practically efficient solution to the problem of an accurate exploration of timing and area trade-offs in optimizing arithmetic circuits with multiple operation trees using CSAs. The application of our approach leads to find a best CSA implementation of circuit in terms of both timing and area. Experimental resluts on a number of digital filter designs show that our algorithm is able to achieve 48% to 84% area saving under timing constraint and 4% to 39% timing reduction under area constraint compared with those produced by the conventional carry-save adder implementations.eng
dc.languageeng-
dc.publisher한국과학기술원-
dc.subjectCSA-
dc.subjectcarry-save-adder-
dc.subject연산최적화-
dc.subject캐리세이브에더-
dc.subjectarithmetic optimization-
dc.titleAccurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders-
dc.title.alternativeCSA를 이용한 회로속도와 면적의 상관관계 정밀측정을 통한 연산최적화-
dc.typeThesis(Master)-
dc.identifier.CNRN165848/325007-
dc.description.department한국과학기술원 : 전산학전공, -
dc.identifier.uid000993124-
dc.contributor.localauthorKim, Tae-Whan-
dc.contributor.localauthor김태환-
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