Generation of cell descriptions from regitster transfer language description for datapath

Abstract

This thesis describes a system, as a part of a silicon compiler, which generates cell descriptions from the register transfer language description of a datapath on a VLSI design. To reduce the complexity of design effort, we devise an algorithm which partitions components of a datapath into manageable subgroups. In order to reduce the area occupied by the wires, we emphasize regularity of interconnection of cells. In this system, the interconnections are defined as a part of cell description and adjacent cells are connected by abutment rather than routing. Furthermore, no huge cell library is needed because a description of a cell can always be generated from the cell description in terms of rectangles and polygons. Cell descriptions obtained by this system can be used to generate the physical layout. This system is implemented in about 2000 lines of "C" code and runs on a VAX-11/780 computer under the UNIX(4.2 BSD) operating system.