AND/OR parallel token machine

Abstract

In this thesis, a parallel token machine for the AND/OR parallelism of a logic programming language is proposed. This machine is composed of limited number of processors, a token pool, a waiting pool, and a common memory. The token pool contains the tokens in the running state and the waiting pool contains the tokens in the waiting state. The common memory stores a program, binding environments, and management information. A token in the token pool or the waiting pool represents the state of a process. As well as an OR parallelism, the parallel token machine exploits an AND parallelism found in a deterministic clause such as divide and conquer algorithms. Therefore, the parallel token machine increases the parallelism as compared with the OR-parallel token machine. A computational model to achieve AND/OR parallelism is presented, and to support that computational model, the machine instruction of the abstract machine and the interpretation cycle of a processor are newly defined.