Fault diagnosis of bit-sliced processor systems

Abstract

A new architecture for fault-tolerant bit-sliced processor is presented in this thesis. This architecture enables us to detect more than one faulty slice in a bit-sliced processor array. For this new architecture, a slightly modified basic cell is presented for easy testing and reconfiguration. Methods of fault detection and fault location suitable for this architecture are also presented. Using a ring-type shorting network for reconfiguration, minimization of propagation time delay among slices is achieved.