Design automation process using hardware description language

Abstract

This thesis suggests an indispensible and basic tools for design automation of a digital system and its design verification. It translates description of the digital system expressed by the hardware description language into a computer executable codes like polish strings or Boolean equations, or logic diagrams. DDL, which is a more hardware oriented language among hardware description languages, is used to describe system components. Finally, this thesis produces a logic diagram which is a gap to be bridged in the design automation area.