(A) study on pipelined, parallel FFT processor

Abstract

The fast Fourier transform (FFT) is an efficient algorithm to compute the discrete Fourier coefficients of a finite sequence of data. In this thesis, a FFT processor is proposed. The proposed processor includes novel design concepts such as the overlapping of arithmetic and memory operations, a simultaneous write-read memory, and pipelined parallel computation of 2 stages of the perfect shuffle network. Control of the processor is implemented by microprogramming technique. It performs a 8-point FFT in 7 $\mu$S at 2-MHz clock rate, and can operate up to a 15-MHz clock. Microprogram control of the system organization provides a flexible processing capability and the pipeline feature provides the maximum utilization of the hardware resources.