(A) study on the image processor memory architecture

Abstract

Image processing operations require that an image or partial image be stored in a memory system that permits access to sequences of image points along any row or column of this image array and/or to the image points within small rectangular areas of the array. In this paper an economic addressing circuitry of such memory system is developed, which separates address calculation and routing. The proposed relative address calculation method improves both cost and complexity of the memory system which can be accessed pq x 1, 1 x pq and/or p x q image subarray simultaneously, where p and q are design parameters.