Digital fault simulation of logic circuits

Abstract

Method of generating a set of test experiments for detection and diagnosis of the logical faults in the digital system have been proposed by many authors. In this dissertation, an algorithm for generating a set of fault diagnostic informations for the digital systems is proposed. The proposed algorithm employes a fault simulation technique, which injects every possible faults, one at a time, to the fault-free machine to determine the behavior of each faulty machine. This algorithm can be applied to the sequential machines as well as the combinational machines. It is implemented in the NOVA 840 computer. The performance of the algorithm is evaluated using a 7400 series 4-bit arithmetic and logic unit and found it to be satisfactory.