DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Kim, Tae-Whan | - |
dc.contributor.advisor | 김태환 | - |
dc.contributor.author | Lyuh, Chun-Gi | - |
dc.contributor.author | 여준기 | - |
dc.date.accessioned | 2011-12-13T05:25:57Z | - |
dc.date.available | 2011-12-13T05:25:57Z | - |
dc.date.issued | 2004 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=237675&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/33203 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전산학전공, 2004.2, [ viii, 92 p. ] | - |
dc.description.abstract | This thesis addresses four important synthesis problems with an objective of minimizing power consumption in system-on-chip (SoC) design. (1) Scheduling and binding problem for power minimization: We solve the problem efficiently by formulating it into the problem of finding a maximum flow of minimum cost in a network; (2) Interconnect synthesis problem with the consideration of coupled transition activity: We solve the problem by simultaneously formulating and solving the following two issues in an integrated fashion: binding data transfers to buses and determining a (physical) order of lines in each bus; (3) Bus encoding with crosstalk delay elimination problem: We solve the problem by analyzing, formulating, and solving the problem of minimizing a weighted sum of the self transition and cross-coupled transition activities on bus; (4) Memory optimization problem for energy minimization: We minimize the energy consumption by scheduling memory accesses and binding memories simultaneously, so that the use of standby mode in memories are maximized. A set of extensive experimental data is provided to confirm the effectiveness of the proposed approaches. | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | BUS ENCODING | - |
dc.subject | BUS BINDING | - |
dc.subject | LOW POWER SYNTHESIS | - |
dc.subject | MEMORY OPTIMIZATION | - |
dc.subject | 메모리 최적화 | - |
dc.subject | 버스 인코딩 | - |
dc.subject | 버스 바인딩 | - |
dc.subject | 저전력 합성 | - |
dc.title | Low power synthesis problems in system-on-chip designs | - |
dc.title.alternative | 시스템-온-칩 설계에서의 저전력 합성 문제 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 237675/325007 | - |
dc.description.department | 한국과학기술원 : 전산학전공, | - |
dc.identifier.uid | 020005188 | - |
dc.contributor.localauthor | Kim, Tae-Whan | - |
dc.contributor.localauthor | 김태환 | - |
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