Motion compensation is a powerful method in video coding to reduce temporal redundancies of successive image frames. The key procedure of motion compensation is motion estimation that traces the motion trajectories of moving objects in a frame. As one of major application of motion compensation, motion-compensated interpolation is very attractive since it can be combined with known coding techniques to reduce the bit rate. Motion-compensated interpolation requires motion estimation to satisfy both an accuracy constraint and a real-time constraint. Although various motion estimation algorithms are endeavoured, block-based approach is widely used in video coding area. However, a typical block-based approach, the block-matching algorithm, can not satisfy the accuracy constraint. The hierarchical block-matching algorithm (HBMA) is quite successful in fulfilling the accuracy constraint because it copes with global motion of moving object and local motion as well. Nevertheless, high computational complexity of HBMA prevents it from satisfying the real-time constraint. Hence the parallel architecture for HBMA is necessary for real-time processing, whereas considerablely less work has been done. However, there are inherent data dependencies in HBMA, which are major obstacles in parallel processing. Data dependencies of HBMA are investigated and defined as interlayer data dependency and intralayer data dependency. This dissertation presents pipelined VLSI architectures for HBMA based on systolic array to achieve real-time processing performance. At first, a generalized pipelined VLSI architecture is proposed. It consists of r stages, each of which corresponds to a layer of HBMA. Each stage has a systolic array for BMA, a bilinear interpolator for bilinear interpolation, and the latch mechanisms for arranging the intermediate results of the motion vectors. Besides, there are internal memories to store image data needed to compute motion vectors. To satisfy data dependenc...