(A) highly concurrent control and data flow computer architecture

Abstract

A highly concurrent control and data flow computer architecture(HCCD) which is proposed for general purpose parallel computing is designed and presented. Also, its two-level program organization and representation are studied. The program organization for the HCCD architecture combines the concepts of data flow computing and control flow computing. The data flow approach at the lower level exploits all the concurrency within each block of instructions without primitive synchronizing operators. The control flow approach at the higher level provides safe executions of the DF-blocks in parallel and sharing of data structures without any complication. It is shown that the control token coloring scheme not only exploits nearly all the potential concurrency in a given program, but also reduces the synchronization problems arising in the conventional MIMD architectures. To synchronize the parallel executions of the DF-blocks with minimum constraints, two types of the DF-blocks, namely, the PDF-and SDF-blocks, are introduced and the activation records are used to exploit more concurrency. The HCCD architecture contains ring structured data flow processing units with a control processor connected to a memory system. The modular and asynchronous nature of the HCCD architecture makes the system design simple. The most significant aspects of the HCCD architecture, i.e., the SDF-block scheduling, the management of the color, the instruction scheduling, etc. are described in detail. Also, the analyses of the HCCD architecture are made in several aspects.