MRF based image processing and segmentation algorithm and its implementation on DSP processor

Abstract

In this thesis a new hierarchical MRF image model for image processing and segmentation is proposed, and the algorithm is implemented on a DSP processor. The architecture of low power MCU with efficient DSP interface and the architecture of DSP processor for image processing are also presented. The proposed MRF model consists of two levels of MRF. The first level is intensity process and the second one is label process. The energy functions for the two random fields are designed as an optimization criterion. For the sake of computational efficiency, a deterministic relaxation algorithm is adopted for optimizing energy function of the intensity process. The label process is optimized through a region merge approach. The tightly coupled information interchange between segmentation procedure and restoration procedure makes the model robust against noises and also makes the segmentation procedure be performed without any a priori knowledge about regions so as to be applied to very large classes of domains. The proposed algorithm is implemented on CalmMedia, which is a VLIW fixed point DSP processor. The original proposed algorithm is modified and simplified to be adequate for DSP implementation. In order to maximize algorithm performance, several optimization techniques such as loop unrolling, loop optimization, and delayed branch are used, and instruction level parallelism is massively pursued. The architecture of low power MCU with efficient DSP interface and the architecture of DSP processors for audio and image processing are proposed and implemented. Some additional image processing algorithms such as camera processing, DCT/IDCT, and ME/MC are described, and simulation results and performance estimation are presented.