DC Field | Value | Language |
---|---|---|
dc.contributor.author | Sang, Haoyang | ko |
dc.contributor.author | Xie, Wenao | ko |
dc.contributor.author | Park, Gwangtae | ko |
dc.contributor.author | Yoo, Hoi-Jun | ko |
dc.date.accessioned | 2024-09-05T11:00:14Z | - |
dc.date.available | 2024-09-05T11:00:14Z | - |
dc.date.created | 2024-08-29 | - |
dc.date.issued | 2024-05 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.71, no.5, pp.2534 - 2538 | - |
dc.identifier.issn | 1549-7747 | - |
dc.identifier.uri | http://hdl.handle.net/10203/322723 | - |
dc.description.abstract | Internet-of-Things (IoT) drives the demand for artificial intelligence (AI) system-on-chips (SoCs) for vast always-on ultra-low power applications such as human action recognition (HAR) for surveillance systems, face detection (FD) and recognition (FR) for home security, etc. Previous AI-IoT SoCs still face limited system efficiency caused by the high leaky power of SRAMs, huge external memory access (EMA), and frequent on-chip data transfer. The proposed ultra-low power RISC-V embedded AI-IoT SoC is composed of 1) a novel bit-line (BL) segmented coupled nvSRAM macro with switchable working modes: SRAM, non-volatile memory (NVM), NVM computing in memory (CIM), performing pre-charge reusing, power gating and local data swapping; 2) a hot-silent encoded (HSE) uDMA cluster with 1MB multi-bank eMRAM to reduce the on-chip transmission power and eliminate the EMA power; 3) and an event-driven wake-up unit (EDWU) for skipping unnecessary inference; 4) a RISC-V core with dedicated ISA extension for switchable working modes. The proposed SoC achieves an energy efficiency of 20.3-35.5 TOPS/W @ResNet-20 (fix-point-8, FXP8) inferencing, which shows a 2.82x - 3.69x efficiency improvement compared to the previous state-of-the-art (SOTA) AI-IoT SoCs. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | An 2.31uJ/Inference Ultra-Low Power Always-on Event-Driven AI-IoT SoC With Switchable nvSRAM Compute-in-Memory Macro | - |
dc.type | Article | - |
dc.identifier.wosid | 001230987700057 | - |
dc.identifier.scopusid | 2-s2.0-85187387193 | - |
dc.type.rims | ART | - |
dc.citation.volume | 71 | - |
dc.citation.issue | 5 | - |
dc.citation.beginningpage | 2534 | - |
dc.citation.endingpage | 2538 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.identifier.doi | 10.1109/TCSII.2024.3374885 | - |
dc.contributor.localauthor | Yoo, Hoi-Jun | - |
dc.contributor.nonIdAuthor | Sang, Haoyang | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Random access memory | - |
dc.subject.keywordAuthor | Common Information Model (electricity) | - |
dc.subject.keywordAuthor | Low-power electronics | - |
dc.subject.keywordAuthor | Face recognition | - |
dc.subject.keywordAuthor | System-on-chip | - |
dc.subject.keywordAuthor | Surveillance | - |
dc.subject.keywordAuthor | System-on-chip (SoC) | - |
dc.subject.keywordAuthor | nvSRAM | - |
dc.subject.keywordAuthor | compute-in-memory (CIM) | - |
dc.subject.keywordAuthor | ultra low power | - |
dc.subject.keywordAuthor | AI-IoT | - |
dc.subject.keywordAuthor | Nonvolatile memory | - |
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