DRAM-based In-memory-computing for high-density and high energy-efficiency AI accelerator

Abstract

This thesis covers research on DRAM-based in-memory computing (IMC) to achieve higher density and efficiency in artificial intelligence (AI) accelerators. Recently, IMC technology has been utilized to achieve higher energy efficiency and throughput on AI beyond digital implementation. However, most previous research uses SRAM-based IMC, which limits the density. We propose a DRAM-based IMC method for two AI accelerator chips to achieve higher density and efficiency than existing digital accelerators and SRAM-IMC. First, DynaPlasia proposes a new solution at the memory cell, cell array, and architecture level. First, at the memory cell level, the impact of leakage current is reduced with a new computation method to improve efficiency and accuracy. Additionally, at the cell array level, a numerical expression method reducing the computing logic switching and a hierarchical in-memory analog-to-digital converter (ADC) further improve the computation efficiency. Lastly, at the architectural level, the processor is dynamically reconfigured to operate with higher efficiency and throughput without wasting resources in various structures of actual AI tasks. In addition, the second chip, Scaling-CIM, proposes a cell array and algorithm-level optimization in addition to DynaPlasia's cell to reduce the analog-to-digital conversion burden. First, we propose a method to reduce the number of bits and operations of the ADC for analog computing by utilizing the characteristics of the partial sum distribution in multi-bit operations. To this end, we propose a hardware structure for cell array that can adjust the conversion scale. Also, at the algorithm level, we propose a method of controlling the conversion scale according to the characteristics of each layer in the AI model. Accordingly, the proposed two AI accelerators with DRAM-based IMC achieved higher throughput and energy efficiency than existing artificial intelligence accelerators in actual deep neural network benchmarks.