DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | 유회준 | - |
dc.contributor.author | Kwon, Hankyul | - |
dc.contributor.author | 권한결 | - |
dc.date.accessioned | 2024-07-30T19:31:48Z | - |
dc.date.available | 2024-07-30T19:31:48Z | - |
dc.date.issued | 2024 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=1097277&flag=dissertation | en_US |
dc.identifier.uri | http://hdl.handle.net/10203/321696 | - |
dc.description | 학위논문(석사) - 한국과학기술원 : 전기및전자공학부, 2024.2,[iii, 17 p. :] | - |
dc.description.abstract | A real-time dense 3D reconstruction on spatial computing is challenging since its memory access surpasses the available memory bandwidth. To solve this problem, the proposed processor integrates two key building blocks – Dilation-based TSDF (D-TSDF) fusion and Block-Projection (BP) engine. D-TSDF projects the depth map in the reverse order of voxel-to-pixel coordinate transformation and dilates it, leading to 96.61%p External Memory Access (EMA) reduction with minimum map quality degradation. Second, a specialized BP engine compresses high-resolution occupancy grid by decomposing the 3D bitmap into 2D and 1D vectors, achieving ×166.09 reduced memory bandwidth. The proposed processor is implemented in 28nm CMOS technology occupying 1.27 mm2 area. As a result, 96.45 fps 3D reconstruction is possible while consuming only 15.94 mW power. | - |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | 3D 재구성▼aTSDF 융합▼a공간 컴퓨팅▼aASIC | - |
dc.subject | 3D reconstruction▼aTSDF fusion▼aSpatial computing▼aApplication specific integrated circuits | - |
dc.title | (A) memory-efficient 3d reconstruction processor with dilation-based tsdf fusion and block-projection cache system for spatial computing | - |
dc.title.alternative | 공간 컴퓨팅을 위한 팽창 기반 TSDF 융합 및 블록-투영 캐시 시스템을 활용한 메모리 효율적 3D 재구성 프로세서 | - |
dc.type | Thesis(Master) | - |
dc.identifier.CNRN | 325007 | - |
dc.description.department | 한국과학기술원 :전기및전자공학부, | - |
dc.contributor.alternativeauthor | Yoo, Hoi-jun | - |
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