Dynamic jitter compensation methods of phase rotator based clock generation systems

Abstract

With the increment of data traffic, demanding high-speed wireline communication has been increased. As a result, the data speed of the Ethernet standard has increased. Multi-channel clock and data recovery circuits have been developed to support high-speed Ethernet data. This paper presents a method to dynamically reduce deterministic jitter occurring in a multi-channel clock and data recovery system. It introduces a dynamic algorithm optimizing the process of compensating for non-linearity in phase rotator using digital mapping functions and removing residual phase through continuous phase correction. Additionally, it enhances the efficiency of residual phase compensation via delay-locked loop circuits and widens the range of compensatable frequency offsets through switches. Through this proposed method, the jitter of recovered clock from 28Gb/s data can be compensated to less than 143fs when the frequency offset ranges from -1200ppm to 1200ppm.