Power integrity design of full wafer scale chip architecture for hyper-scale artificial intelligence training and inference computing

Abstract

In this paper, we propose, for the first time, a full wafer scale chip architecture design considering power integrity for hyper-scale artificial intelligence training and inference computing. To ensure the power integrity of the proposed full wafer scale chip, we designed and modeled a hierarchical power distribution network and verified it by comparing it with 3D electromagnetic simulation results. Furthermore, we set a current spectrum-based target impedance for the modeled power distribution network of the full wafer scale chip. Additionally, we analyzed the simultaneous switching noise in the proposed power distribution network and applied a decoupling capacitor design methodology considering this noise. Finally, by analyzing the impedance and simultaneous switching noise in the power distribution network with the decoupling capacitor design applied, we verified whether the power integrity of the proposed full wafer scale chip is satisfied.