Memory-side cache-based rowhammer protection scheme

Abstract

The continuous advancement of DRAM technology has significantly increased memory capacity and performance, but it has also introduced challenges related to reliability. The Rowhammer threat has been demonstrated to have severe implications, including system crashes, and elevation of attacker process privileges. The increasing vulnerability of newer DRAM generations raises the seriousness of the Rowhammer threat even further. This study introduces an innovative memory-side cache-based mitigation against Rowhammer at-tacks that is uncontrolled by the CPU and is applicable to any DDR-based memory systems. We explore the design space of creating an entirely cache-based mitigation and, also, analyze the possibility of combining the cache with in-DRAM Rowhammer mitigations. We show that, although cache-only Rowhammer prevention has no performance overhead compared to the prior works, it has a significant hardware overhead for low Rowhammer threshold values, diminishing its attractiveness. However, the combination of the memory-side cache and Mithril, a prior work, is demonstrated to be effective in both reducing the overall hardware overhead of the cache and reducing the performance degradation of Mithril from 7.3% to 3% at the Rowhammer threshold of 256.