Study on fast, reliable, and variation-tolerant near-memory stateful logic via majority gate

Abstract

With the arrival of the Fourth Industrial Revolution and advances in technologies such as artificial intelligence, the amount of data to be computed is expected to increase dramatically, reaching 181 zettabytes by 2025. However, the traditional computing structure, the von Neumann architecture, is not well suited for memory-intensive computations due to bottlenecks in the data in-out process. Memristor-based in-memory computing, called Stateful logic, is an emerging candidate for solving von Neumann bottleneck problem. Experimental demonstration of various Arithmetic logic operations including 16 boolean logic gates so far validates their potential as a computing unit for future paradigms. However, few studies are interested in the inherent stochasticity of memristor during logic operations, leading to inaccurate operation, and more susceptible to multi-input logic gates. Here, we propose a novel near-memory computing via three-input Majority logic, satisfying these demands for practical implementation in the crossbar array. We increased the practicality of logic gates by engineering an intrinsic series resistance component in the device. Then, we experimentally demonstrated both 1-bit Full Adder and Full Subtractor operations in 5 steps using 7 devices without data loss. Spatio-temporal efficiency of 1-bit FA operation with our Majority logic is about 35% more efficient than the latest Boolean logic. Furthermore, we propose an efficient data manipulation methodology and demonstrate Parallel Prefix adder, which is one of the fastest adders due to its maximized parallelism, using that methodology, resulting in log scale latency of operation.