Development of high performance logic and memory devices using germanium and silicon-germanium channel

Abstract

This dissertation focuses on the development of the logic and memory device using germanium (Ge), which has a higher carrier mobility than silicon (Si), to overcome the limitation of Si channel and the scaling for device integration. The first purpose of this work is to overcome the limitation of device scaling by using Ge channel in logic device. The second purpose of this work is to increase the channel mobility by using Ge to polycrystalline Si (poly-Si) to solve the problem of cell current reduction, which is one of the serious problems in 3D vertical NAND (V-NAND) flash memory. As a study of Ge channels for the application to logic device, a gate stack with extremely low equivalent oxide thickness (EOT) below 0.6 nm was developed showing a superior interface and low gate leakage current. First, a plasma oxidation process was performed at room temperature to form a germanium oxide (GeO$_2$) with excellent dielectric properties while having a very thin physical thickness of 0.3 nm. In addition, a dielectric having high dielectric constant appropriate for Ge channels was presented. The Y$_2$O$_3$ is known as a well-matched dielectric to Ge, but it shows relatively low dielectric constant of 10. To apply a high compatibility of Y$_2$O$_3$ with Ge and GeO$_2$, the Y was doped into ZrO$_2$, which is a high-k dielectric, showing a high dielectric constant of 48 at a thickness of 3.7 nm. In addition, H$_2$ high pressure annealing was carried out to improve the interface characteristics. As a result, a gate stack having am extremely thin EOT of 0.57 nm was formed by using a GeO$_2$, Y doped ZrO$_2$ (Y-ZrO$_2$), and H$_2$ high pressure annealing. In particular, the interface trap density (Dit) was 3.4 × 10$^{11}$ eV$^{-1}$cm$^{-2}$, which means outstanding interface properties, and the gate leakage current was 4.5 × 10$^{-6}$ A/cm$^2$, which was 1000 to 10000 times lower than other studies reported so far. This result indicates that Y-ZrO$_2$ with H$_2$ high pressure annealing shows outstanding Dit and gate leakage current.The second study is to increase the channel mobility of poly-Si channel using Ge for 3D V-NAND flash memory. In this study, to increase the channel mobility, two effects of were confirmed when applying Ge with poly-Si channel: an improvement in channel mobility by applying intrinsic Ge mobility, and an additional improvement in channel mobility by increasing the grain size in poly-Si during solid-phase crystallization using additional Ge layer. By optimizing the Ge diffusion profile in this channel, the channel mobility was increased up to 32% without the degradation of the interface properties. In addition, the channel mobility was further increased to 101%, by increasing the grain size using Ge. Because an amorphous Ge has lower crystallization temperature than an amorphous Si, the use of Ge can be effective to increase the grain size and reduce the thermal budget for crystallization. By applying this technique to the NAND flash memory, the speed of memory operation was increased without deterioration of the retention or endurance characteristics.In conclusion, we proposed a method to overcome the limitation of device scaling for logic and memory device using Ge, which represents that it is a breakthrough technology for further development of semiconductor technology.