Hardware and algorithm co-optimization for graph neural network acceleration

Abstract

As Graph Neural Networks (GNNs) have emerged as a mainstream algorithm in many research areas, designing a GNN accelerator becomes a new challenge. Compared to previous DNNs, GNNs include characteristics of both graph processing and neural networks. In this paper, we analyze the workload of GNNs executed on existing hardware platforms and identify the intensive DRAM access as the main bottleneck for accelerating GNNs. Focusing on this problem, we propose a series of schemes, both hardware and algorithm side, to reduce DRAM access. Our work achieves on average 3.67x, 5.36x, 3.49x speedup than the GPU on GCN, SAGE, and GAT.