Design of energy-efficient rail-to-rail-input paralleled amplifier

Abstract

For fast buffering of large stepwise input to an nF-range capacitive load, this paper presents a 5-V rail-to-railinput/output paralleled-amplifier in which a dynamic class-C amplifier (DCCA) and a linear single-stageoperational transconductance amplifier (OTA) are combined in parallel. During slew time, the DCCA, which isdesigned to consume a near-zero static current, dominantly supplies the dynamic current up to 8.5 mA to theoutput. When the output gets closer to the fine-settling region, the DCCA is rapidly faded out in virtue of adedicated near-zero dead-zone control (NDZC), and it hands over to the linear OTA. A current-redistributive railto-rail Gm-boosting technique is also proposed so that the OTA can have a wide gain-bandwidth product (GBW)even over the rail-to-rail input range while minimizing the quiescent current dissipation. The prototype chip wasfabricated only with 0.5-μm 5-V CMOS devices, and it occupies a die area of 0.03 μm2. The proposed amplifierconsumed a static current of 3.1 μA with a supply voltage of 5 V. The slew rates with load capacitances (CL) of0.8 and 10 nF were measured to be 10.3 and 0.86 V/μs, respectively, for a step input of Δ4.2 V, which is a stateof-the-art result compared to prior chips. The measured GBW of 10 – 127 kHz was achieved over 0.8 – 10 nF CLwith ≥ 59° phase margin. The measured GBW deviation in a common-mode voltage (VCM) range of 0.3 to 4.7 Vwas within the maximum of 20%.