DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Choong-Ki | ko |
dc.contributor.author | Phadke, Omkar | ko |
dc.contributor.author | Kim, Tae-Hyeon | ko |
dc.contributor.author | Kim, Myung-Su | ko |
dc.contributor.author | Yu, Ji-Man | ko |
dc.contributor.author | Yoo, Min-Soo | ko |
dc.contributor.author | Choi, Yang-Kyu | ko |
dc.contributor.author | Yu, Shimeng | ko |
dc.date.accessioned | 2024-06-20T07:00:18Z | - |
dc.date.available | 2024-06-20T07:00:18Z | - |
dc.date.created | 2024-04-05 | - |
dc.date.issued | 2024-05 | - |
dc.identifier.citation | IEEE ELECTRON DEVICE LETTERS, v.45, no.5, pp.929 - 932 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | http://hdl.handle.net/10203/319895 | - |
dc.description.abstract | A capacitive synaptic transistor (synaptor) compatible with the fabrication process of conventional Flash memory is proposed for compute-in-memory (CIM) array cells to support energy-efficient inference operations. This synaptor demonstrates the highly reliable endurance characteristic of program/erase (P/E) due to overturned charge injection occurring between a control gate (CG) and a floating gate (FG) rather than between the FG and a channel. On- and off- state capacitances (C-on and C-off) are determined by the area ratio of CG and FG. After optimizing the pulse conditions, we achieved the P/E endurance of at least 10(7) cycles and retention time of 10(4) sec. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Capacitive Synaptor With Overturned Charge Injection for Compute-in-Memory | - |
dc.type | Article | - |
dc.identifier.wosid | 001211581100047 | - |
dc.identifier.scopusid | 2-s2.0-85189500895 | - |
dc.type.rims | ART | - |
dc.citation.volume | 45 | - |
dc.citation.issue | 5 | - |
dc.citation.beginningpage | 929 | - |
dc.citation.endingpage | 932 | - |
dc.citation.publicationname | IEEE ELECTRON DEVICE LETTERS | - |
dc.identifier.doi | 10.1109/LED.2024.3382497 | - |
dc.contributor.localauthor | Choi, Yang-Kyu | - |
dc.contributor.nonIdAuthor | Phadke, Omkar | - |
dc.contributor.nonIdAuthor | Kim, Tae-Hyeon | - |
dc.contributor.nonIdAuthor | Yoo, Min-Soo | - |
dc.contributor.nonIdAuthor | Yu, Shimeng | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | In-memory computing | - |
dc.subject.keywordAuthor | Capacitance-voltage characteristics | - |
dc.subject.keywordAuthor | Logic gates | - |
dc.subject.keywordAuthor | Flash memories | - |
dc.subject.keywordAuthor | Capacitance | - |
dc.subject.keywordAuthor | Temperature measurement | - |
dc.subject.keywordAuthor | Junctions | - |
dc.subject.keywordAuthor | Compute-in-memory | - |
dc.subject.keywordAuthor | floating gate | - |
dc.subject.keywordAuthor | capacitive synapse | - |
dc.subject.keywordAuthor | cycling endurance | - |
dc.subject.keywordAuthor | retention | - |
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