DC Field | Value | Language |
---|---|---|
dc.contributor.author | Cho, Byung-Jin | ko |
dc.contributor.author | Shin, Sungwon | ko |
dc.contributor.author | Shin, Euijoong | ko |
dc.date.accessioned | 2024-01-12T01:15:46Z | - |
dc.date.available | 2024-01-12T01:15:46Z | - |
dc.identifier.uri | http://hdl.handle.net/10203/317776 | - |
dc.description.abstract | Semiconductor devices may include a stacked structure including interlayer insulating layers and gate electrodes alternately stacked in a vertical direction, a core region extending in the vertical direction in the stacked structure, a channel layer on a side surface of the core region and facing the gate electrodes and the interlayer insulating layers, a first dielectric layer, a data storage layer and a second dielectric layer, which are between the channel layer and the gate electrodes in order, and an anti-ferroelectric layer including a portion interposed between the first dielectric layer and a first gate electrode of the gate electrodes. The second dielectric layer may contact the channel layer. The anti-ferroelectric layer may be formed of an anti-ferroelectric material having a tetragonal phase. | - |
dc.title | Memory semiconductor devices comprising an anti-ferroelectric material | - |
dc.title.alternative | 반 강유전성 물질을 포함하는 메모리 반도체 장치 | - |
dc.type | Patent | - |
dc.type.rims | PAT | - |
dc.contributor.localauthor | Cho, Byung-Jin | - |
dc.contributor.assignee | KAIST, Samsung Electronics Co.,Ltd. | - |
dc.identifier.iprsType | 특허 | - |
dc.identifier.patentApplicationNumber | 17316777 | - |
dc.identifier.patentRegistrationNumber | 11744082 | - |
dc.date.application | 2021-05-11 | - |
dc.date.registration | 2023-08-29 | - |
dc.publisher.country | US | - |
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