A 2.5mW 12MHz-BW 69dB SNDR Passive Bandpass ΔΣ ADC with Highpass Noise-Shaping SAR Quantizers

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dc.contributor.authorOh, Seinko
dc.contributor.authorPark, Seungako
dc.contributor.authorJung, Yoontaeko
dc.contributor.authorKoo, Jiminko
dc.contributor.authorCho, Dongheeko
dc.contributor.authorHa, Sohmyungko
dc.contributor.authorJe, Minkyuko
dc.date.accessioned2023-12-04T07:02:06Z-
dc.date.available2023-12-04T07:02:06Z-
dc.date.created2023-11-29-
dc.date.issued2023-06-11-
dc.identifier.citation2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)-
dc.identifier.urihttp://hdl.handle.net/10203/315687-
dc.description.abstractA 4th-order passive bandpass Δ Σ modulator (BPDSM) using a 2- path transformation structure is presented. The proposed BPDSM replaces a power-hungry resonator with a z-to-z2-transformed passive loop filter. The prototype bandpass Δ Σ ADC provides a wide intermediate frequency (IF) range of 1.25MHz to 60MHz. The measured SNDR is 69dB with a power consumption of 2.5mW at 12MHz bandwidth when its highest sampling rate is 240MS/s.-
dc.languageEnglish-
dc.publisherIEEE-
dc.titleA 2.5mW 12MHz-BW 69dB SNDR Passive Bandpass ΔΣ ADC with Highpass Noise-Shaping SAR Quantizers-
dc.typeConference-
dc.identifier.scopusid2-s2.0-85167589309-
dc.type.rimsCONF-
dc.citation.publicationname2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)-
dc.identifier.conferencecountryJA-
dc.identifier.conferencelocationKyoto-
dc.identifier.doi10.23919/vlsitechnologyandcir57934.2023.10185342-
dc.contributor.localauthorJe, Minkyu-
dc.contributor.nonIdAuthorPark, Seunga-
dc.contributor.nonIdAuthorJung, Yoontae-
dc.contributor.nonIdAuthorKoo, Jimin-
dc.contributor.nonIdAuthorCho, Donghee-
dc.contributor.nonIdAuthorHa, Sohmyung-
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EE-Conference Papers(학술회의논문)
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