A 7–8.5 GHz LC Voltage-Controlled Oscillator with –111.7 dBc/Hz Phase Noise at 1-MHz offset for Ultra-Low-Jitter Phase-Locked Loop

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This work presents an area efficiency LC voltage-controlled oscillator for an ultra-low-jitter phase-locked loop. Using a 3-turn area-compact spiral, the VCO achieve area-efficient without degrading LC-tank quality factor. The negative transconductance cell was NMOS type so that the start-up was done in 3ns. This work also includes a tail inductor for the noise filtering. As a result, the measured phase noise at 8 GHz was -111.7 dBc/Hz with 1 MHz offset and -134.9 dBc/Hz with 10 MHz offset. The power consumption was only 2.7 mW at 8 GHz. Also, the die area was less than 0.03 mm2.
Publisher
한국과학기술원 반도체설계교육센터
Issue Date
2023-01
Language
English
Citation

IDEC Journal of Integrated Circuits and Systems, v.9, no.1, pp.1 - 5

DOI
10.23075/jicas.2023.9.1.001
URI
http://hdl.handle.net/10203/315595
Appears in Collection
EE-Journal Papers(저널논문)
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