DC Field | Value | Language |
---|---|---|
dc.contributor.author | Hwang, Chan woong | ko |
dc.contributor.author | Park, Hangi | ko |
dc.contributor.author | Lee, Yongsun | ko |
dc.contributor.author | Seong, Taeho | ko |
dc.contributor.author | Choi, Jaehyouk | ko |
dc.date.accessioned | 2023-12-01T02:00:24Z | - |
dc.date.available | 2023-12-01T02:00:24Z | - |
dc.date.created | 2023-12-01 | - |
dc.date.issued | 2023-10 | - |
dc.identifier.citation | IDEC Journal of Integrated Circuits and Systems, v.9, no.4, pp.37 - 43 | - |
dc.identifier.uri | http://hdl.handle.net/10203/315533 | - |
dc.description.abstract | This work presents a low-jitter ring-oscillator-based digital PLL (RO-DPLL). To achieve low jitter, the proposed RO-DPLL used calibration techniques to optimize the gain of the Proportional-path (P-path) and Integral-path (I-path) in the digital-loop-filter (DLF) simultaneously. Since the effect of flicker noise increases as the frequency increases, the frequency drift of the RO-DPLL becomes more severe in the operation of the RO-DPLL. Thus, it is critical to calibrate the gain of the I-path to an optimal value because I-path of DLF compensates for the frequency error of the PLL. Moreover, the optimally-spaced time-to-digital-converter (OS-TDC) with the threshold calibrator provides sufficient information, supporting the efficient operation of the calibrators. Due to the use of the P/I-path co-optimization (PICO) and OS-TDC with calibrator, the proposed RO-DPLL achieved the rms jitter of 343 fs and the reference spur of –65dBc. And, its FoMjitter,N was –258.5 dBc, comparable to the state-of-the-art RO-based analog PLLs. | - |
dc.language | English | - |
dc.publisher | 한국과학기술원 반도체설계교육센터 | - |
dc.title | A Low-jitter Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Optimally Spaced TDC for Flicker-Noise Reduction | - |
dc.type | Article | - |
dc.type.rims | ART | - |
dc.citation.volume | 9 | - |
dc.citation.issue | 4 | - |
dc.citation.beginningpage | 37 | - |
dc.citation.endingpage | 43 | - |
dc.citation.publicationname | IDEC Journal of Integrated Circuits and Systems | - |
dc.identifier.doi | 10.23075/jicas.2023.9.4.008 | - |
dc.identifier.kciid | ART002999466 | - |
dc.contributor.localauthor | Choi, Jaehyouk | - |
dc.contributor.nonIdAuthor | Lee, Yongsun | - |
dc.contributor.nonIdAuthor | Seong, Taeho | - |
dc.description.isOpenAccess | N | - |
dc.subject.keywordAuthor | Ring digitally-controlled oscillator (RDCO) | - |
dc.subject.keywordAuthor | digital phase-locked-loop (DPLL) | - |
dc.subject.keywordAuthor | time-to-digital converter (TDC) | - |
dc.subject.keywordAuthor | proportional-path | - |
dc.subject.keywordAuthor | integral-path | - |
dc.subject.keywordAuthor | digital-loop filter (DLF) | - |
dc.subject.keywordAuthor | rms jitter | - |
dc.subject.keywordAuthor | flicker noise | - |
dc.subject.keywordAuthor | thermal noise | - |
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