Neuro-CIM: ADC-Less Neuromorphic Computing-in-Memory Processor With Operation Gating/Stopping and Digital-Analog Networks

Abstract

A highly energy-efficient neuromorphic computing-in-memory (Neuro-CIM) processor is proposed for ultralow-power deep learning applications. Neuro-CIM can support spiking neural network (SNN) to eliminate the power and area overhead of previous CIM processor. The sign extended bits gating reduces the bitline (BL) voltage switching rate due to negative small-magnitude weights allowing 38% power reduction at 8-b weight condition and 25% at 4-b weight condition. In addition, Neuro-CIM replaces high-precision analog-to-digital converter (ADC) with 1-b comparator by exploiting the characteristic of the SNN, and thus, power and area efficiencies are significantly enhanced. Furthermore, the early stopping scheme terminates unnecessary neuronal operations, reducing power consumption by 31%. In addition, the analog and digital networks are integrated for high reconfigurability and energy efficiency. The analog network with voltage folding circuit enables accurate analog-domain aggregation by increasing the dynamic range without compromising the voltage resolution. The digital network-in-memory supports input-output channel extension for high reconfigurability and input data reuse scheme for reducing input memory (IMEM) access. Neuro-CIM is fabricated in 28-nm CMOS technology and occupies the 2.9-mm(2) die area. It achieves the state-of-the-art energy consumption per classification of 0.72 mu J and 92.1% accuracy for CIFAR-10 with 4-b input and 4-b weight and 372.2 mu J and 65.8% accuracy for ImageNet with 6-b input and 8-b weight at 200 MHz, and 1.1-V conditions. Moreover, the proposed CIM processor achieves 310.37 tera operations per second/watt (TOPS/W) and 90.7% accuracy with 4-b input and 1-b weight for Canadian Institute for Advanced Research, 10 classes (CIFAR-10) classification.