A Process-Scalable Ultra-Low-Voltage Sleep Timer With a Time-Domain Amplifier and a Switch-Less Resistance Multiplier

Abstract

The on-chip sleep timer is a compact and cost-effective solution that provides high-precision temperature accuracy through the use of a lookup table (LUT) and dedicated temperature sensor (TS). However, maintaining energy efficiency while integrating an accurate sleep timer is challenging due to the significant increase in leakage currents with process scaling and temperature. The proposed sleep timer overcomes these limitations by utilizing an ultra-low-voltage (ULV) frequency locked-loop (FLL) architecture, a time-domain amplifier (TDA), and a switch-less resistance multiplier (SLRM) with a gate leakage-leveraging technique. The prototype integrated circuit (IC), fabricated in a 65-nm CMOS, achieves a 2.73-ppm/C-? temperature dependency with calibration based on an LUT while consuming only 63 nW at a 0.4-V supply and producing a 180-kHz frequency.