DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Hee Sung | ko |
dc.contributor.author | Jang, Tae Hwan | ko |
dc.contributor.author | Kim, Joon Hyung | ko |
dc.contributor.author | Park, Chul Soon | ko |
dc.date.accessioned | 2023-10-25T01:01:20Z | - |
dc.date.available | 2023-10-25T01:01:20Z | - |
dc.date.created | 2023-08-22 | - |
dc.date.issued | 2023-10 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.31, no.10, pp.1629 - 1633 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | http://hdl.handle.net/10203/313765 | - |
dc.description.abstract | In this study, we present a low-phase-noise 20-GHz phase locked loop (PLL) with simultaneous gm-boosted and third-harmonic impedance-tuned voltage-controlled oscillator (VCO). The proposed PLL is implemented using the 65-nm CMOS technology. By both implementing a cross-coupled center-tapped inductor and controlling the harmonic impedance, the phase noise is improved by approximately 3.4 dB. An auxiliary cross-coupled pair (CCP) is used to boost the transconductance, while a parallel quarter-wave open stub is added to minimize the second-harmonic impedance for the output signal as the squared waveform. The proposed PLL demonstrated a measured phase noise of - 102.05 dBc/Hz at a 1-MHz offset frequency. Based on the measured phase noise, the proposed PLL can achieve a figure of merit (FOM) of - 174.35 dBc/Hz, while it consumes 23.6 mW with a supply voltage of 1 V. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Low-Phase-Noise 20-GHz Phase-Locked Loop Using Harmonic-Tuned VCO Assisting With g(m) -Boosting Technique | - |
dc.type | Article | - |
dc.identifier.wosid | 001043485400001 | - |
dc.identifier.scopusid | 2-s2.0-85165868912 | - |
dc.type.rims | ART | - |
dc.citation.volume | 31 | - |
dc.citation.issue | 10 | - |
dc.citation.beginningpage | 1629 | - |
dc.citation.endingpage | 1633 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.identifier.doi | 10.1109/TVLSI.2023.3294404 | - |
dc.contributor.localauthor | Park, Chul Soon | - |
dc.contributor.nonIdAuthor | Jang, Tae Hwan | - |
dc.contributor.nonIdAuthor | Kim, Joon Hyung | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | 20 GHz | - |
dc.subject.keywordAuthor | CMOS | - |
dc.subject.keywordAuthor | frequency synthesizer | - |
dc.subject.keywordAuthor | LC oscillator | - |
dc.subject.keywordAuthor | low phase noise | - |
dc.subject.keywordAuthor | low power | - |
dc.subject.keywordAuthor | phase-locked loop (PLL) | - |
dc.subject.keywordAuthor | voltage-controlled oscillator (VCO) | - |
dc.subject.keywordPlus | FREQUENCY-SYNTHESIZER | - |
dc.subject.keywordPlus | CMOS | - |
dc.subject.keywordPlus | RECEIVER | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.