Multiplier-less IIR filter synthesis algorithms to trade-off the delay and the number of adders

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dc.contributor.authorKang, H.-J.-
dc.contributor.authorPark, In-Cheol-
dc.date.accessioned2008-02-21T06:16:31Z-
dc.date.available2008-02-21T06:16:31Z-
dc.date.created2012-02-06-
dc.date.issued2001-05-06-
dc.identifier.citationIEEE International Symposium on Circuits and Systems (ISCAS 2001), v.2, no., pp.693 - 696-
dc.identifier.issn0271-4310-
dc.identifier.urihttp://hdl.handle.net/10203/3129-
dc.languageENG-
dc.language.isoen_USen
dc.publisherIEEE-
dc.titleMultiplier-less IIR filter synthesis algorithms to trade-off the delay and the number of adders-
dc.typeConference-
dc.identifier.scopusid2-s2.0-0034998484-
dc.type.rimsCONF-
dc.citation.volume2-
dc.citation.beginningpage693-
dc.citation.endingpage696-
dc.citation.publicationnameIEEE International Symposium on Circuits and Systems (ISCAS 2001)-
dc.identifier.conferencecountryAustralia-
dc.identifier.conferencecountryAustralia-
dc.contributor.localauthorPark, In-Cheol-
dc.contributor.nonIdAuthorKang, H.-J.-

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