Enhanced Long Edge First Routing Algorithm and Evaluation in Large-Scale Networks-on-Chip

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Networks-on-Chip (NoCs) have been developed to be the on-chip interconnects of many-core systems. Routing is one of the most important factors that determine NoC performance. In this paper, we enhance LEF (Long Edge First), a routing algorithm proposed for the commonly used 2D meshes. LEF chooses one of the two dimension-ordered routing algorithms (XY or YX) for each packet based on the relative position between the source node and the destination node. LEF avoids deadlock by restricting the use of certain virtual channels (VCs). In particular, one VC of each channel in the X (Y) dimension is reserved exclusively for packets routed with the YX (XY) algorithm. However, we found that it is not necessary to restrict the use of VCs in both X and Y dimensions. We prove that restricting the use of VCs in only one dimension is enough for deadlock avoidance. In this way, the VCs in one dimension can be allocated to any packet. We also modify the method of choosing XY or YX routing to further improve the VC utilization.Our evaluation using a fast and cycle-accurate FPGA-based NoC simulator shows that, in small-scale NoCs (8x8 and 16x8), the enhanced LEF (LEF++) outperforms both the original LEF and the dimension-ordered routing algorithms. Under a uniform traffic, LEF++ achieves a maximum of 6% improvement of throughput than LEF. Under a non-uniform traffic, LEF++ also performs better than LEF and provides up to 36.7% higher throughput than the dimension-ordered routing algorithms. The FPGA-based NoC simulator enables us to investigate how the routing algorithms behave in large-scale NoCs with thousands of nodes. Like in small-scale NoCs, both LEF and LEF++ can achieve higher throughputs than the dimension-ordered routing algorithms under the hotspot traffic. However, we observe a phenomenon that does not occur in small-scale NoCs. Large-scale NoCs adopting LEF/LEF++ are generally unstable at extremely high loads. This is evident in that simulation results of small-scale NoCs cannot be applied directly to large-scale NoCs.
Publisher
IEEE
Issue Date
2017-09
Language
English
Citation

2017 IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), pp.83 - 90

DOI
10.1109/mcsoc.2017.22
URI
http://hdl.handle.net/10203/312325
Appears in Collection
RIMS Conference Papers
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