Decoupled address translation for heterogeneous memory systems

Abstract

The support for the heterogeneous memory in the conventional virtual memory has an inherent problem. For the efficient translationin the critical translation lookaside buffers (TLBs), the page size hasbeen growing. However, the heterogeneous memory managementrequires a nimble fine-grained migration mechanism to quicklymove necessary memory portions to the precious fast memory. Toaddress the challenges posed by the conflicting goals in the heterogeneous memory support, this paper proposes to decouple theaddress translation into a two-step process. The decoupling resolvesthe conflict as the critical core-side TLBs perform the translationto an intermediate address space, and the memory-side translationprovides the actual physical location of the memory devices.