A Hybrid Dual-Path Step-Down Converter with 96.2% Peak Efficiency Using a 250m μ Large-DCR Inductor

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dc.contributor.authorHuh, Yeunheeko
dc.contributor.authorShin, Se-Unko
dc.contributor.authorHong, Sung-Wanko
dc.contributor.authorWoo, Young-Jinko
dc.contributor.authorJu, Yong-Minko
dc.contributor.authorChoi, Sung-Wonko
dc.contributor.authorCho, Gyu-Hyeongko
dc.date.accessioned2023-08-08T08:03:48Z-
dc.date.available2023-08-08T08:03:48Z-
dc.date.created2023-07-07-
dc.date.created2023-07-07-
dc.date.issued2018-06-
dc.identifier.citation32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018, pp.225 - 226-
dc.identifier.urihttp://hdl.handle.net/10203/311251-
dc.description.abstractA dual-path step-down converter (DPNC) is presented for achieving high power efficiency in mobile PMICs. The proposed DPNC supplies a load current (ILOAD) via two parallel paths using a hybrid structure with one inductor and one flying capacitor, solving an intrinsic problem of conventional buck converter topology (CBT) which is a significant power loss from a large DCR of inductor (RDCR). Therefore, DPNC not only achieves a high efficiency, but also reduces a heating problem. Additionally, DPNC can shrink a volume of PMIC set with a low manufacturing cost, by alleviating a RDCR specification of inductor. Although a 250mΩ of large-Dcr inductor was used, this paper achieved a 96.2% of peak-efficiency, and the total loss from parasitic resistance of external components was reduced to up to 30% compared to CBT. Furthermore, DPNC achieved much higher efficiency not only in a wide ILOAD range, but also in a wide VOUT/VIN range.-
dc.languageEnglish-
dc.publisherInstitute of Electrical and Electronics Engineers Inc.-
dc.titleA Hybrid Dual-Path Step-Down Converter with 96.2% Peak Efficiency Using a 250m μ Large-DCR Inductor-
dc.typeConference-
dc.identifier.wosid000853983300089-
dc.identifier.scopusid2-s2.0-85056826198-
dc.type.rimsCONF-
dc.citation.beginningpage225-
dc.citation.endingpage226-
dc.citation.publicationname32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018-
dc.identifier.conferencecountryUS-
dc.identifier.conferencelocationHonolulu-
dc.identifier.doi10.1109/VLSIC.2018.8502284-
dc.contributor.localauthorCho, Gyu-Hyeong-
dc.contributor.nonIdAuthorHong, Sung-Wan-
dc.contributor.nonIdAuthorWoo, Young-Jin-
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EE-Conference Papers(학술회의논문)
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