Modeling, simulation and measurement of on-chip interconnects with extremely thin Si substrate for flexible electronics

Abstract

In this paper, on-chip interconnections with an ultra-thin silicon (Si) chip for flexible electronics is modeled and verified through 3D EM simulation and measurement. To achieve flexibility of the chip, we grind a Si substrate to 15 μm. When the Si substrate is extremely thin, the lossy Si substrate effect can be reduced. Moreover, we place a ground plane on the top of the Si substrate to further reduce the Si loss. The interconnection lines are designed with the HFSS 3D EM simulation by changing design variables with 50 ohm matching impedance. In addition, we conduct an equivalent circuit modeling of the interconnection line based on RLGC components. The insertion loss (S21) result of the model is then verified with the simulation and measurement results when we ignore the effect of the Si substrate. Finally, the modeling result showed good correlation with the simulation and measurement. From the experiments, we conclude that the flexible chip can be modeled with the simple interconnection RLGC model when the Si thickness is extremely thin and well designed.