Signal Integrity Analysis of Through-Silicon Via (TSV) With a Silicon Dioxide Well to Reduce Leakage Current for High-Bandwidth Memory Interface

Abstract

In this article, we propose and analyze a through silicon via (TSV) with a silicon dioxide well (SDW) to reduce leakage current in the design of a high-speed signaling and low-power consumption high-bandwidth memory (HBM) interface. In the proposed TSV, the SDW is inserted into the silicon substrate area between TSVs. By inserting the SDW, the silicon substrate's effective conductivity and permittivity are lowered compared to a conventional TSV. The proposed TSV with the SDW improves insertion loss by up to 0.079 dB at 4 GHz by minimizing the leakage current. In addition, by reducing the effective permittivity of the silicon substrate, the difference in ratio between the capacitive coupling and inductive coupling is minimized. It is also possible to obtain a reduction in far-end crosstalk (FEXT) in the range of HBM interface signaling. RLGC modeling of the proposed TSV with the SDW is presented and is physically analyzed based on the frequency-dependent equivalent capacitance and conductance of the silicon substrate. The proposed TSV with SDW is finally evaluated using an eye diagram, and the eye height and width improved by up to 13.7% and 4.7% at 8 Gb/s, respectively, compared to the conventional TSV. The proposed TSV also reduced dynamic power consumption by 48.1% at 8 Gb/s, verifying the low-power structure.