Exploring Ways to Minimize Dropout Voltage for Energy-Efficient Low-Dropout Regulators: Viable approaches that preserve performance

Abstract

Low-dropout (LDO) regulators are ideal off-chip and on-chip solutions for powering noise-sensitive loads, such as phase-locked loops, analog-to-digital converters, and sensor interfaces, because they convert voltage through a linear operation with no output voltage ripples. Wide bandwidth is one of the performance benefits of LDO regulators that lead to rapid transient response and superior power supply rejection (PSR). Furthermore, LDO regulators offer several advantages over switch-mode dc-dc converters, including a smaller die area and a more compact footprint (since they do not necessitate bulky passive components). Unfortunately, LDO regulators suffer from an inescapable disadvantage: poor power conversion efficiency (PCE); this is dominantly due to a considerable dropout voltage (V DO), which is the input-to-output differential voltage and applied across the pass transistor delivering output current. A small V DO to improve efficiency, on the other hand, tends to drastically lower LDO regulators' feedback loop gain, thereby causing a significant performance drop in aspects of PSR and voltage regulation performance. Because of this, most LDO regulators have been designed and developed with a large V DO, leading many to view them as an inefficient part of the power management system. There is a wealth of tutorial literature that explains the fundamental principle of LDO regulators operating with a sufficient dropout voltage [1], [2], [3], [4], [5], [6], [7], [8]. To the contrary, this article explores effective ways to extremely minimize the dropout voltage, without losing regulator performance, toward the realization of energy-efficient LDO regulators.