DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Lee, Sang-Gug | - |
dc.contributor.advisor | 이상국 | - |
dc.contributor.author | Xu, Jinglong | - |
dc.date.accessioned | 2023-06-26T19:34:33Z | - |
dc.date.available | 2023-06-26T19:34:33Z | - |
dc.date.issued | 2022 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=1008380&flag=dissertation | en_US |
dc.identifier.uri | http://hdl.handle.net/10203/310002 | - |
dc.description | 학위논문(석사) - 한국과학기술원 : 전기및전자공학부, 2022.8,[iii, 37 p. :] | - |
dc.description.abstract | This dissertation discusses the design of CMOS receivers (RX) for two applications: (i) high performance 5G NR and (ii) low power wide area network (LPWAN) Internet-of-Things (IoT). For 5G application, an n79 (4.4 GHz - 5.0 GHz) variable gain LNA is presented. To offer a wide gain range while preserving good linearity with minimum power dissipation at lower gain modes, the proposed LNA adopted three key techniques: (i) imbalanced current bleeding, (ii) drain-side DC current switching and (iii) bleeding with an adaptive biasing scheme. The proposed LNA shows a peak gain of 20.5 dB with a 0.74 dB minimum NF, with a 13.4 dB gain control range while reducing the power down to 4.2 mW at the lowest gain mode. The proposed adaptive biasing improves the IIP3 by 4 dB. As a result, this LNA work achieves the best FoM1 among reported LNAs operating at 4-6 GHz. In addition, for LPWAN IoT application, a multi-band ultra-low-power binary frequency-shift keying (BFSK) RX is presented. For the front-end of the RX, it adopted a resistive feedback LNA with a tunable passive matching gain covering 0.2 - 1.0 GHz. The N-path filter based 50%-to-25% duty-cycle conversion mixer can further offer a 5-dB passive voltage gain. A frequency-to-energy BFSK demodulator is adopted with multi-channel selectivity. The proposed RX measured a -96 dBm sensitivity with 295 uW dissipated. This RX is compatible with the state-of-the-art reconfigurable Data/Wake-up RX architecture and is ready for SoC integration with digital-intensive back-end processing. | - |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | 5G NR▼aLow Power Wide Area Network▼aReceiver▼aLow Noise Amplifier▼aUltra-Low Power | - |
dc.subject | 5G 신규무선▼a저전력 광역통신망▼a수신기▼a저소음 증폭기▼a초저전력 | - |
dc.title | Design of CMOS receivers for 5G NR and LPWAN applications | - |
dc.title.alternative | 5G NR 및 LPWAN 응용을 위한 CMOS 수신기 설계 | - |
dc.type | Thesis(Master) | - |
dc.identifier.CNRN | 325007 | - |
dc.description.department | 한국과학기술원 :전기및전자공학부, | - |
dc.contributor.alternativeauthor | 허경룡 | - |
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