Area-efficient check node architecture for 5G LDPC decoders

Abstract

A min-sum algorithm (MSA) reduces a hardware complexity of a belief propagation algorithm (BPA), but at the cost of error correcting performance. And, an improved offset min-sum (IOMS) algorithm has been proposed to improve the error correcting performance, but additional areas are needed due to a check node unit (CNU) which consist of the searching module (SM) finding the two minima and the normalization and offset blocks improving the performance. In this paper, we present area-efficient architectures without error correcting performance degradation in the CNU. The proposed methods have 0.08dB decoding loss compared to the conventional 5G LDPC, but reduce the CNU area by 35%. In order to reduce the area, the second minimum, which is relatively less important than the first minimum, is efficiently found in the SM. In addition, the normalization computation is expressed as an approximate signed digit (ASD) which represents up to two non-zero digits and making it a multiplier-less block. Furthermore, this normalization block and offset block are replace with a carry save adder (CSA) to make it hardware friendly.