Design and analysis of signal and power integrity for multi-layer scramble PCB connecting different types of packages다중 패키지타입의 모바일 디램을 위한 스크램블회로기판의 신호 무결성과 전력 무결성 분석 및 설계에 대한 연구
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | Kim, Joungho | - |
| dc.contributor.advisor | 김정호 | - |
| dc.contributor.author | Kim, Taewon | - |
| dc.date.accessioned | 2023-06-26T19:33:43Z | - |
| dc.date.available | 2023-06-26T19:33:43Z | - |
| dc.date.issued | 2023 | - |
| dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=1032853&flag=dissertation | en_US |
| dc.identifier.uri | http://hdl.handle.net/10203/309846 | - |
| dc.description | 학위논문(석사) - 한국과학기술원 : 전기및전자공학부, 2023.2,[v, 36 p. :] | - |
| dc.description.abstract | In order to evaluate dozens of types of multi-package types of mobile DRAM, a scramble circuit board that connects the package types between the DRAM and the processor is required. To improve the signal integrity and power integrity of the scrambled circuit board, it can be solved by changing the material, but it is not a sensible answer in terms of cost. Therefore, in this thesis, we will investigate how to improve the signal integrity and power integrity of the scrambled circuit board, propose and verify the combination method of the signal and power layer applied with the improvement plan. | - |
| dc.language | eng | - |
| dc.publisher | 한국과학기술원 | - |
| dc.subject | Signal integrity▼apower integrity▼ascramble PCB▼amulti-package type | - |
| dc.subject | 신호 무결성▼a전력 무결성▼a스크램블회로기판▼a다중 패키지타입 | - |
| dc.title | Design and analysis of signal and power integrity for multi-layer scramble PCB connecting different types of packages | - |
| dc.title.alternative | 다중 패키지타입의 모바일 디램을 위한 스크램블회로기판의 신호 무결성과 전력 무결성 분석 및 설계에 대한 연구 | - |
| dc.type | Thesis(Master) | - |
| dc.identifier.CNRN | 325007 | - |
| dc.description.department | 한국과학기술원 :전기및전자공학부, | - |
| dc.contributor.alternativeauthor | 김태원 | - |
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- EE-Theses_Master(석사논문)
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