High-bandwidth on-chip interconnect covert channel in GPUs

Abstract

As GPUs are becoming widely deployed in the cloud infrastructure to support different application domains, the security concerns of GPUs are becoming increasingly important. Specifically, the support for multiprogramming in modern GPUs has led to new vulnerabilities because we can execute multiple kernels in a GPU at the same time. In this thesis, we propose a new microarchitectural timing covert channel for GPUs, which can be established based on the shared on-chip interconnect channels. In particular, we first reverse-engineer the organization of the on-chip networks in modern GPUs to understand the core placements throughout the GPU. The hierarchical organization of the GPU results in the sharing of interconnect bandwidth between neighboring cores. Based on this organization, we identify how contention for the interconnect bandwidth can be exploited for a novel covert channel attack. We propose two types of interconnect-based covert channels that exploit the on-chip network hierarchy. Unlike cache-based covert channels, in our interconnect-based covert channel, no states of the on-chip network need to be modified for communication and the impact of contention is very predictable. By exploiting the parallelism of GPUs, our proposed covert channel results in very high bandwidth -- achieving approximately 24 Mbps of bandwidth on NVidia Volta GPUs, approximately 6x higher bandwidth compared to previously proposed GPU covert channels.