Time-interleaved hybrid two-step ADC sharing VTC and TDC reference in second stage

Abstract

Analog-to-Digital Converter (ADC) for the radar system requires high-speed and low-power operation. Time-interleaved architecture is a necessary structure for high-speed and low-power performance by using multiple slow ADCs as sub-ADCs. Mismatches between channels which is the bottleneck of time-interleaved structure, causes interleaving spurs in frequency spectrum and degrades ADC performance. In previous works, they used high—cost calibration logic or just manually tuned each channel to reduce mismatches between channels. In this paper, a new structure is proposed to reduce these channel mismatches minimizing manual tuning. The proposed structure is a two-step ADC and high-speed and low-power performance is realized by using both the voltage domain and the time domain.