(A) 4-channel high-voltage-compliance stress-free neural stimulation IC in standard CMOS process

Abstract

Staking low-voltage devices is a promising technique to overcome the limitation of supply voltage that allows the system to possibly operate at the voltage much higher than the standard process’s rating voltage. In this thesis, by utilizing this technique, a neural stimulator is designed with a supply voltage up to 4 times of rating voltage, 4VDD. Proposed dynamic switching buffer and adaptive offset generator are presented to overcome the high-voltage (HV) issues under the operation of the stacking driver while improve the performance of the stimulator with better charge balancing and higher compliance voltage.