Design of ultra-low jitter, high-frequency clock generators using power-gating injection locking techniques

Abstract

Recently, as the data rate increases rapidly in both wireless and wireline communication systems, exploring ultra-low-jitter and high-frequency clock generators is becoming increasingly important. An injection-locked clock multiplier (ILCM) is one of the clock generator architectures that can achieve excellent jitter performance. However, the conventional ILCM structures cannot have a large multiplication factor (N) since the injection strength of an ILCM decreases as N increases. It is thus difficult to generate high-frequency signals. To solve this problem, in this thesis, we introduce power-gating ILCM (PG-ILCM) that can have a large value of N above 100 or more. Utilizing PG-ILCM, two architectures were proposed, for wireless and wireline applications. First, an LC oscillator based 100 GHz phase-locked loop (PLL) was proposed for wireless communication, especially beyond 5G systems. Second, a ring oscillator based 8 GHz ILCM was proposed for wireline communication, especially for area-efficient SoC. Both architectures achieved excellent performance with RMS jitter of under 100 fs.