Coherent RF transceiver for broadband waveguide links assisted by baseband phase locked loop광대역 도파관 링크용 기저대역 위상동기회로를 활용한 동기식 RF 송수신기

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This paper presents an 86.71875GHz RF transceiver IC featuring a fully integrated clock and data recovery (CDR)-assisted carrier recovery loop (CRL) with on-chip clock generation for waveguide links. The test chip fabricated in 28nm CMOS demonstrates 57.8125Gb/s PAM-4 data transmission over a 1.5m waveguide channel and 28.90625Gb/s NRZ data transmission over a 3m waveguide channel. The proposed CRL is implemented only by using a base-band CDR without using power-and-area-hungry RF circuit blocks due to the baseband-synchronized carrier frequency in which means an LO frequency is three times the null frequency of the baseband signal. The CDR-assisted CRL improves the measured timing margin of the recovered 28.90625Gb/s NRZ signal at a bit error rate (BER) of 10$^{-12}$ by more than 38% compared to the conventional case. Thanks to the small hardware overhead of the all-digital baseband circuity in the proposed CRL, the proposed link achieves an FoM of 3.5pJ/b/m showing state-of-the-art performance in terms of throughput-distance, and energy efficiency.
Advisors
Bae, Hyeon-Minresearcher배현민researcher
Description
한국과학기술원 :전기및전자공학부,
Publisher
한국과학기술원
Issue Date
2023
Identifier
325007
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2023.2,[v, 45 p. :]

Keywords

RF transceiver▼aIntegrated circuit▼aClock and data recovery▼aCarrier recovery loop▼aPhase-locked loop▼aDelay-locked loop▼aWaveguide▼aAntenna▼aHigh-speed wireline communication; 무선 송수신기▼a직접회로▼a클록 및 데이터 복원▼a반송파 복원루프▼a위상 고정루프▼a지연 고정루프▼a도파관▼a안테나▼a고속 유선 통신

URI
http://hdl.handle.net/10203/309128
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=1030529&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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