Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques

Cited 1 time in webofscience Cited 0 time in scopus
  • Hit : 226
  • Download : 0
DC FieldValueLanguage
dc.contributor.authorMoon, Byeong-Taekko
dc.contributor.authorYun, Byeonghunko
dc.contributor.authorKim, Jusungko
dc.contributor.authorLee, Sang-Gugko
dc.date.accessioned2023-05-13T04:03:02Z-
dc.date.available2023-05-13T04:03:02Z-
dc.date.created2023-05-12-
dc.date.created2023-05-12-
dc.date.issued2023-
dc.identifier.citationIEEE ACCESS, v.11, pp.34942 - 34951-
dc.identifier.issn2169-3536-
dc.identifier.urihttp://hdl.handle.net/10203/306798-
dc.description.abstractThis article presents a power-efficient frequency doubler employing gain boosting and harmonic-enhancing techniques. With a single transistor only, the gain boosting technique can reach the maximum achievable gain (G(max)) by adding embedded passive components, thereby obtaining high voltage swings. Then, the transistor's nonlinearity is essential, which is maximized by the harmonic transition scheme of the transistor operation along with high voltage swings. In addition, a harmonic reflector and a harmonic leakage canceller are employed for the second harmonic enhancement. The harmonic reflector prevents unwanted harmonic mixing by minimizing the incoming second harmonic current fed back to the input. The harmonic leakage canceller suppresses the leakage loss of the second harmonic current present at the output. Furthermore, thanks to a proposed dual-band output matching network, the output impedance is conjugately matched to achieve the G(max) at the fundamental frequency while it is matched to extract the second harmonic output power simultaneously. To verify the proposed techniques, the prototype was designed as a single-stage circuit that does not require additional amplifying stages, which led to higher power efficiency and lower chip area. Implemented in a 65-nm CMOS process, the measurement results show a saturated output power of 0.9 dBm and 3-dB bandwidth of 26 GHz (237-263 GHz), respectively, while requiring a chip area of 0.071 mm(2). Total power efficiency, including the effect of injected signal power, is 2.87 % while consuming only 37 mW dc power.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleAnalysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques-
dc.typeArticle-
dc.identifier.wosid000972158200001-
dc.identifier.scopusid2-s2.0-85153392613-
dc.type.rimsART-
dc.citation.volume11-
dc.citation.beginningpage34942-
dc.citation.endingpage34951-
dc.citation.publicationnameIEEE ACCESS-
dc.identifier.doi10.1109/ACCESS.2023.3264531-
dc.contributor.localauthorLee, Sang-Gug-
dc.contributor.nonIdAuthorKim, Jusung-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorHarmonic analysis-
dc.subject.keywordAuthorTransistors-
dc.subject.keywordAuthorBoosting-
dc.subject.keywordAuthorPower generation-
dc.subject.keywordAuthorVoltage-
dc.subject.keywordAuthorPower harmonic filters-
dc.subject.keywordAuthorPower amplifiers-
dc.subject.keywordAuthorCMOS-
dc.subject.keywordAuthordual-band matching network-
dc.subject.keywordAuthorfrequency multiplier-
dc.subject.keywordAuthorharmonic reflector-
dc.subject.keywordAuthormaximum achievable gain-
dc.subject.keywordAuthornonlinearity-
dc.subject.keywordAuthorterahertz-
dc.subject.keywordPlusOUTPUT POWER-
dc.subject.keywordPlus65-NM CMOS-
dc.subject.keywordPlusNOISE-
dc.subject.keywordPlusOSCILLATOR-
dc.subject.keywordPlusAMPLIFIER-
dc.subject.keywordPlusELEMENTS-
Appears in Collection
EE-Journal Papers(저널논문)
Files in This Item
There are no files associated with this item.
This item is cited by other documents in WoS
⊙ Detail Information in WoSⓡ Click to see webofscience_button
⊙ Cited 1 items in WoS Click to see citing articles in records_button

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0