DC Field | Value | Language |
---|---|---|
dc.contributor.author | Bae, Hyungjoon | ko |
dc.contributor.author | Hyun, Yujin | ko |
dc.contributor.author | Kim, Suchang | ko |
dc.contributor.author | Park, Sangsoo | ko |
dc.contributor.author | Lee, Jaeyoung | ko |
dc.contributor.author | Jang, Boseon | ko |
dc.contributor.author | Choi, Suyoung | ko |
dc.contributor.author | Park, In-Cheol | ko |
dc.date.accessioned | 2023-02-14T07:00:17Z | - |
dc.date.available | 2023-02-14T07:00:17Z | - |
dc.date.created | 2023-01-05 | - |
dc.date.created | 2023-01-05 | - |
dc.date.created | 2023-01-05 | - |
dc.date.created | 2023-01-05 | - |
dc.date.created | 2023-01-05 | - |
dc.date.issued | 2023-03 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON COMPUTERS, v.72, no.3, pp.893 - 899 | - |
dc.identifier.issn | 0018-9340 | - |
dc.identifier.uri | http://hdl.handle.net/10203/305172 | - |
dc.description.abstract | This paper presents a high-speed counter architecture associated with novel LFSR state extension. By employing the proposed state extension, an Undefined control sequence \emph-bit LFSR counter with (2m−1) states is modified to cover 2m states without degrading the counting rate. Based on the property that only the low-order bits are frequently switched, the proposed counter consists of two sub-counters to achieve a high counting rate and reduce the hardware complexity needed to convert an LFSR state into a binary state. The low-order sub-counter is implemented with the proposed LFSR counter, and the high-order sub-counter is designed by employing the conventional synchronous binary counter. In addition, the implemented counter takes into account the speed degradation caused by the large fan-out of the high-order sub-counter. The proposed counter designed with standard cells operates at 2.08 GHz in a 65 nm CMOS technology, and its counting rate is almost independent of the counter size. | - |
dc.language | English | - |
dc.publisher | IEEE COMPUTER SOC | - |
dc.title | High-Speed Counter with Novel LFSR State Extension | - |
dc.type | Article | - |
dc.identifier.wosid | 000932835000023 | - |
dc.identifier.scopusid | 2-s2.0-85133796964 | - |
dc.type.rims | ART | - |
dc.citation.volume | 72 | - |
dc.citation.issue | 3 | - |
dc.citation.beginningpage | 893 | - |
dc.citation.endingpage | 899 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON COMPUTERS | - |
dc.identifier.doi | 10.1109/TC.2022.3187343 | - |
dc.contributor.localauthor | Park, In-Cheol | - |
dc.contributor.nonIdAuthor | Hyun, Yujin | - |
dc.contributor.nonIdAuthor | Park, Sangsoo | - |
dc.contributor.nonIdAuthor | Lee, Jaeyoung | - |
dc.contributor.nonIdAuthor | Jang, Boseon | - |
dc.contributor.nonIdAuthor | Choi, Suyoung | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Arithmetic and logic units | - |
dc.subject.keywordAuthor | combinational logic | - |
dc.subject.keywordAuthor | high-speed arithmetic | - |
dc.subject.keywordAuthor | sequential circuits | - |
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